The present invention relates to programmable logic integrated circuitry devices and, more particularly, the present invention relates to hybrid multipliers implemented in programmable logic integrated circuitry devices having integrated DSP (“DSP”) circuitry.
Programmable logic devices (“PLDs”) are well known as shown in, for example, Jefferson et al. U.S. Pat. No. 6,215,326 and Ngai et al. U.S. Pat. No. 6,407,576. PLD technology is well known for its ability to allow one common hardware design (embodied in an integrated circuit) to be programmed to meet the needs of many different applications. PLDs with a given hardware design can be manufactured in large quantities at low cost. Each user then programs PLDs of that kind to meet that user's particular needs. The user does not have to do a custom integrated circuit design, with the attendant high cost, delay, and difficulty of revision if modifications are subsequently needed.
One of the problems facing users of PLDs is the limited logic capacity of any particular PLD. As applications become more complex, the logic resources and their interconnections in a PLD become limiting factors in the ability to implement particular designs in the PLD. This is at least partially attributable to the fact that a relatively large portion of programmable logic and interconnections are typically used to implement signal or data processing tasks (e.g., digital signal processing (“DSP”) tasks) that would otherwise require comparatively few resources if implemented using DSP circuitry.
In an attempt to help alleviate this problem, recently, PLDs have been manufactured that include, in addition to programmable logic components, DSP components that implement common DSP tasks. Such common DSP tasks include, for example, multiplication. However, the multipliers implemented in the DSP circuitry of PLDs are not optimized for all types of multiplication tasks. For example, the multipliers embedded in the DSP circuitry of any particular PLD are limited to one or more particular sizes (e.g., 9 bits by 9 bits, 18 bits by 18 bits, 36 bits by 36 bits, etc.).
In order to multiply data having sizes that do not conform with one of the available sizes, present-day hardware compilers implement such a multiplication operation in a single multiplier that would be able to accommodate such a multiplication. This results in inefficient use of resources. For example, when compiling a 10 bits by 10 bits multiplication when only 9 bits by 9 bits multipliers and 18 bits by 18 bits multipliers are available, the 18 bits by 18 bits multiplier would be used, thus making inefficient use of a larger multiplier.
It would therefore be desirable to provide a more efficient implementation of multipliers embedded in the DSP circuitry that is integrated in PLDs.